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Shenzhen, China · Service

Signal and power integrity

We simulate before you fabricate — and tell you which channel is marginal while it can still be changed.

What this solves

  1. A board came back and the link will not train, with no way to tell whether it is the channel, the package or the part.

  2. The design passes DRC and still fails compliance, because nothing checked the loss budget.

  3. Rails look fine on a scope and the processor still resets under simultaneous switching.

Outcomes

What is different afterwards

Deliverables are the artefacts you receive. These are the things that are true once the work is done.

  1. A marginal channel is identified while the layout can still be changed, not after fabrication

  2. A link that will not train can be attributed — channel, package or part — instead of guessed at

  3. The decoupling is placed against a measured PDN profile rather than a rule of thumb

Datasheet

What we have actually shipped

Every figure here is one already delivered on a published project. Check your requirement against it before you write to us.

Channel analysis
S-parameter extraction, TDR, insertion and return loss
Receiver analysis
Eye diagram and jitter at the receiver, worst-case channel
Crosstalk
Densest region, under simultaneous-switching conditions
Power
PDN impedance profile with the decoupling it implies
Thermal
Steady-state simulation where the power stage warrants it
Tools
Mentor HyperLynx, Keysight ADS
Method

How we work on this

What we actually do

Simulation exists to move discovery earlier. A channel that closes in simulation may still surprise you; a channel that fails in simulation will certainly fail on the bench, and finding that out before fabrication costs a week instead of a revision.

Signal integrity

We extract S-parameters for the channels that matter and check them against the insertion loss budget for the standard in question, then run eye and jitter analysis at the receiver for the worst case rather than the typical one.

Power integrity

PDN impedance analysis across the supply rails drives decoupling placement, rather than decoupling being placed by habit and checked afterwards. Simultaneous-switching noise is modelled where the escape density makes it plausible.

Rescue work

This is also the entry point for boards that already exist. If a link will not close or a rail will not hold, we audit the design as it stands and deliver a findings report with a fix plan — see design review and rescue.

A time-domain reflectometry trace on a network analyser, with the board and its calibration standard connected
Time-domain reflectometry locating a discontinuity along the channel, while the layout can still change.

What you receive

Every engagement ends with a complete handover. The design is yours.

  • S-parameter models for every high-speed channel, checked against the relevant budget
  • Eye-diagram and jitter analysis at the receiver for the worst-case channel
  • Crosstalk analysis of the densest region under simultaneous-switching conditions
  • PDN impedance profile with the decoupling placement it implies
  • A findings report naming what is marginal, why, and what to change

Work in this area

1 published
18 layers28,400 pins24 Gbps

Super-computer mainboard

Gen4 PCIe at 24 Gbps across an 18-layer board — first fabrication passed signal integrity sign-off.

Read the case study →
Questions

What buyers ask us first

Answered here rather than on a call, because the answer does not change and your time is worth more than a discovery meeting.

We already have a layout. Is it too late?
No — reviewing an existing layout is a normal engagement. It is cheaper than a respin and considerably cheaper than a compliance failure, and the findings report names what is marginal and what to change.
What do we actually receive?
Models, results and a findings report that names what is marginal, why, and what to change. Not a folder of screenshots — a document someone can act on.
Our board passes DRC. Is that not enough?
DRC checks manufacturability, not the loss budget. A board can pass every design rule and still fail compliance because nothing checked whether the channel closes.

Platforms we work with

  • Mentor HyperLynx
  • Keysight ADS
  • S-parameter extraction
  • TDR
  • Eye diagram and jitter
  • Crosstalk and reflection modeling
  • PDN impedance
  • Thermal simulation

Next step

Send us the hard part.

A schematic, a spec, or a rough idea. We’ll come back within one business day with an honest read on feasibility, risk and timeline.