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Industry

Computing and networking

PCIe Gen3/Gen4 backplanes, DDR4 memory subsystems and server mainboards at the density where routing becomes the problem.

Scope

What we build in this sector

Product types we have designed, not a list of everything the sector contains.

  • Server and supercomputer mainboards
  • Backplanes and high-density interconnect
  • Accelerator and NIC carrier boards
  • Board management and telemetry subsystems
Why it is hard

What separates this sector

The constraints that decide the design here, and that a general-purpose electronics supplier tends to meet for the first time on your project.

A high-speed board connected to a network analyser showing an eye diagram and an S-parameter trace
Every Gen4 channel checked against its budget before the board is released.

The layer budget is spent before the routing starts

A high pin-count package consumes most of the stack-up on escape routing alone. What is left has to carry every Gen4 link, and that arithmetic decides the board before anyone opens a layout tool.

A respin costs a quarter, not a week

Tooling, lamination and assembly lead times on a board this size mean a failed link is measured in months. Everything that can be checked in simulation is checked in simulation.

Thermal and power integrity are one problem

Simultaneous switching on a dense board moves the rails and heats the plane at the same time. Treating the PDN and the thermal profile separately is how a board passes both reviews and still resets under load.

Detail

How we approach it

At this density the difficulty is not any individual link. It is that escape routing consumes the layer budget before the long traces are placed, and that the layer count which closes the links is also the one that determines whether the board is affordable.

What this usually involves

  • Stack-ups built around impedance targets rather than a chosen layer count
  • Gen4 links where intra-pair skew has to be compensated at the via, not by serpentining
  • Management and compute domains separated so low-speed switching noise stays out of the high-speed reference planes
  • Full simulation against the loss budget before release, and a DFM review with the fabricator before that
Compliance context

What the product is judged against

We design against these and produce the evidence a submission needs. Certification is held by whoever owns the product, not by us — any supplier who tells you otherwise is describing a different arrangement than the one you are buying.

  • PCI Express CEM (Gen3 / Gen4)
  • JEDEC DDR3 / DDR4 / DDR5
  • IEEE 802.3 (Ethernet)
  • FCC Part 15 / CISPR 32 (emissions)

Published work

1 published
18 layers28,400 pins24 Gbps

Super-computer mainboard

Gen4 PCIe at 24 Gbps across an 18-layer board — first fabrication passed signal integrity sign-off.

Read the case study →
Capabilities

Services most often used here

The same six capabilities, in the combination this sector usually needs.

Building something in this space?

Tell us what the product has to do and where it has to survive. We will come back within one business day with an honest read on feasibility, risk and timeline.

Start a projectSee published work