What we actually do
We build the stack-up around impedance targets first and let the layer count fall out of that, rather than picking a layer count and hoping the links close. Every high-speed signal layer gets paired reference planes, and no high-speed routing runs adjacent to a split plane.
Density
High pin-count devices spend most of the layer budget on escape routing before a single long trace is placed. The order of work matters: escape strategy and stack-up are settled together, at the start, because discovering the layer count was wrong after placement means starting again.
Timing margin
At 24 Gbps there is almost no room for intra-pair skew. We compensate at the via transition rather than serpentining the trace, which keeps the matched section short and away from the connector field. Back-drilling removes stub resonance on the high-speed vias.
Before release
A layout goes to the fabricator with a DFM review, not over the wall. Stack-up tolerance and back-drill depth are agreed with the people who will actually build it — which is considerably easier when they are half an hour away.
