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FPGA and signal processing

RTL for video pipelines, protocol bridges and real-time control — including the multi-FPGA boards that carry them.

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What this solves

  1. A video pipeline needs to run deterministically at rate, and software cannot meet the latency.

  2. Two subsystems speak protocols that do not meet, and the bridge has to be transparent to both.

  3. The RTL exists but nobody can say whether it closes timing, because there is no verification to speak of.

Outcomes

What is different afterwards

Deliverables are the artefacts you receive. These are the things that are true once the work is done.

  1. The pipeline runs deterministically at rate, with a timing report that says so

  2. Resource utilisation is known, so a later feature request can be answered honestly rather than optimistically

  3. The software team gets integration notes written for them, not a bitstream and a shrug

Datasheet

What we have actually shipped

Every figure here is one already delivered on a published project. Check your requirement against it before you write to us.

Families
Xilinx Artix, Kintex, Ultrascale
Languages
Verilog, SystemVerilog, VHDL
Toolchains
Vivado, Quartus, Libero
Verification
Self-checking testbenches that run without hardware
Sign-off
Timing closure report with the critical paths explained
Interfaces
SDI, MIPI, genlock PLL, protocol bridging
Method

How we work on this

What we actually do

FPGA work on this team is rarely an isolated block of RTL. It usually arrives attached to a board with a difficult stack-up, a video standard with unforgiving timing, and a software team who will have to drive the result.

Video and broadcast

SDI and HD decoding, genlock PLL, and multi-FPGA video routing where a single device cannot carry the fabric. Broadcast work is unusual in that the failure mode is public, so the verification bar is set by what happens on air rather than by what passes on a bench.

Protocol bridging and control

Bridges between interfaces that do not natively meet, and real-time control loops where the determinism a processor cannot promise has to come from fabric instead.

Verification

A testbench that runs without hardware is not optional. Timing closure is reported with the critical paths named, so a later change can be assessed rather than attempted and reverted.

An FPGA carrier board on the bench with an eye diagram and a frequency response displayed behind it
A pipeline is not finished when it compiles. It is finished when it holds rate on hardware.

What you receive

Every engagement ends with a complete handover. The design is yours.

  • RTL source in Verilog, SystemVerilog or VHDL, with a testbench that runs without hardware
  • Timing closure report and constraints, with the critical paths explained
  • Resource utilisation, so a later feature request can be answered honestly
  • Bitstream build that is reproducible from a clean checkout
  • Integration notes for the software team that has to drive it
Questions

What buyers ask us first

Answered here rather than on a call, because the answer does not change and your time is worth more than a discovery meeting.

Can you take on RTL somebody else wrote?
Yes. The first thing we build is a testbench, because inheriting RTL with no verification means nobody can say whether a change broke something until the hardware says so.
Do you design the board as well as the RTL?
Both, and that is usually the point of asking us. A multi-FPGA board and the RTL it carries are one problem — splitting them across two suppliers moves the hard part into the gap between them.
How do we know it closes timing?
The timing closure report ships with the RTL, and the critical paths are explained rather than listed. A report nobody can read is not evidence.

Platforms we work with

  • Xilinx Artix
  • Xilinx Kintex
  • Xilinx Ultrascale
  • Vivado
  • Quartus
  • Libero
  • Verilog
  • SystemVerilog
  • VHDL
  • SDI
  • MIPI
  • Genlock PLL

Next step

Send us the hard part.

A schematic, a spec, or a rough idea. We’ll come back within one business day with an honest read on feasibility, risk and timeline.

Start a projectBook a 30-minute technical callRequest our standard NNN agreement