Super-computer mainboard

A computing hardware manufacturer developing a dual-socket compute node for HPC deployment. Client name withheld under NDA.

The customer had an existing board concept but no in-house team with experience routing Gen4 differential pairs at this density.

Density. A 4094-position SP3 processor socket, DDR4 DIMM sockets, M.2 and SC3 modules, plus a BMC subsystem — 28,400 pins on one board. Escape routing alone consumed most of the available layer budget.

Gen4 timing. 24 Gbps links leave almost no margin for propagation-delay skew between the two halves of a differential pair. Standard serpentine length-matching introduces its own discontinuities at this rate.

Stack-up economics. Every added layer raises cost and lamination risk. The customer needed the lowest layer count that would still close the links.

• Built the stack-up around impedance targets first, not layer count. Eighteen layers with paired reference planes for every high-speed signal layer, and no high-speed routing adjacent to a split plane.
• For Gen4 escapes, used intra-pair skew compensation at the via transition rather than trace serpentining, keeping the matched section short and away from the connector field.
• Separated the BMC and management network domain from the compute fabric with its own power island, so low-speed switching noise never entered the PCIe reference planes.
• Applied back-drilling on all Gen4 vias to remove stub resonance in the upper frequency band.

• Signal integrity sign-off passed on the first fabricated build
• Layer count held at 18
• Complete design package handed over: Altium source, Gerbers, stack-up spec, simulation reports, BOM with qualified alternates